Posted by mepian 4 days ago
https://collection.sciencemuseumgroup.org.uk/objects/co85650...
Vanilla architecture won out over all that machine-level cleverness.
Are there any modern CPUs that do what RISC did and the instructions were directly implemented in circuitry, bypassing microcode translation?
I almost would like CPUs to offer programmable microcode layers at this point (yes, easier said than done) so some cores could be dedicated to emulation at the microcode level. The last major ISA switch was Apple's from x86 to ARM. But it would probably be better to just get an FPGA as part of the embarrassment of riches in chip silicon.
You know, an FPGA could be rebranded as an AI processor for the hype train. I think the AI hype they are blathering about in current processors is just vector processing that the video cards do better anyway, but I haven't bothered to parse the propaganda.
ARM, mostly. Instructions are 32 bits wide and aligned on 4-byte boundaries. This simplifies instruction decode. IA-32 does not require this, leading to considerable complexity in superscalar instruction fetch and decode.
The ARM instruction set isn't very "reduced" any more.[1] Despite this, on larger CPUs, most instructions in modern CPUs have direct hardware implementations. There are enough transistors available to do it that way.
[1] file:///home/john/Downloads/arm_instruction_set_reference_guide_100076_0100_00_en.pdf
ARM implementations that support both ARMv7 (both ARM mode and THUMB mode) and ARMv8 also need some kind of translation in the front-end, but recent ARMs (like Apple's implementations) don't support 32-bit mode and are simpler in that way.
Most other ISAs are much closer to the metal, although many implementations still do some level of translation in the front-end (mostly fusing/splitting certain instruction combinations for better efficiency). Examples: ARMv8+, RISC-V, MIPS, Loongson, TI 6x & 7x DSP, and of course most GPUs (and my own MRISC32 ISA).