Easy RISC-V - Hacker News

Posted by todsacerdoti 10/27/2025

Easy RISC-V(dramforever.github.io)

401 points | 80 commentspage 2

bigprovolone 10/28/2025|

if you're looking for an nice RISCV emulator try RARS https://github.com/TheThirdOne/rars

doublerabbit 10/27/2025||

Within the basic "123" ASM demo, I get that x10 - Becomes 0x00000123 as we are taking the integer of x0 and applying 123 to end of it but why is the sp (x2) register at 0x40100000?

What is that sp? Is it important? Why isn't that at 0x000000? Why isn't that explained? That's when I get lost.

ajxs 10/27/2025|

'sp' is the 'stack pointer' register. There's an explanation of the stack later in the guide: https://dramforever.github.io/easyriscv/#the-stack

ks2048 10/28/2025||

This looks great. I like how it starts with a dump of all the instructions we'll be using.

Does anyone know of a complete list, machine readable? e.g.

instructions = [{"name": "lui", "description": "load upper immediate", "args": [...]}, ...]

LarsDu88 10/28/2025||

Great work! I was wondering about this after trying out Easy6502. It would be nice to have a more visual component like Easy6502 which has a draw buffer and snake game tho :)

brucehoult 10/30/2025|

That's one of the first things I suggested to the author ... RV32I has a lot more registers to display than 6502, so I guess there was no room for the graphics output display.

Maybe doing RV32E plus a graphics output would be a good compromise. Sixteen registers is probably enough for any program people are likely to write in this --- and you can tell GCC/LLVM to generate for RV32E if you want to compile C code and paste the asm in. (I'm not sure whether the assembler can actually cope with that)

lachlanj 10/28/2025||

Has anyone seen anything similar to this for x86?

adgjlsfhk1 10/28/2025|

making this in x86 would be fairly tricky since there isn't the same sort of unified core (there used to be, but that was the 16 bit extension set which isn't how x86 is used now).

ReFruity 10/28/2025||

I like this. Do you have a link to your simulator code? I might borrow for a personal project of mine if it's ok.

klelatti 10/28/2025|

https://github.com/dramforever/easyriscv/blob/main/emulator....

ge96 10/28/2025||

tangent I want to link back to this https://github.com/mortbopet/Ripes

Ethan312 10/28/2025|

Nice project. RISC-V tools like this make learning architecture concepts much easier. It’s great to see more hands-on resources that help people move from theory to actual CPU behavior.