links to this entertainment: https://crackhead.technology/anjoy-ssc338q-libtools/

> To me, this issue doesn’t seem as embarrassing as Intel’s wrong CPUIDs. Pipelined CPUs are hard to build

I disagree. Misspelling a name in the CPUID is kind of easy to do, somewhat awkward to test (in a non-tautological way), and pretty easy to work around.

Having `mul ...; lw ...;` fail show that they've done very little testing of the chip. Any basic randomised pipeline testing would hit that trivial case.

Essentially all CPUs are pipelined today. In-order pipelined CPU execution semantics are not particularly hard to test. Even some open source testing systems could detect this bug, e.g. TestRig or RISCV-DV.

[flagged]

Writing software in embedded processor pipelines for bugs in the IT81202 CPU.

Microcode errata re-writes to GPR, compiling low level "mul," and "output," CPU RISC V to system archictecture.