For the PMOS, the output toggles between 1 and 0 (opposite the gate) as expected. However, for the NMOS, the output is always 0.

I don't understand why GND pulls VDD down to 0 for the NMOS, but not the PMOS.

- Made timed minigames optional (e.g. binary tables)

- Added 7 (optional) intro levels to walk through pmos and nmos transistors

- Fixed the bug in the capacitor levels

- Changed editor bg to use dots instead of lines to fix wire confusion

One note: It isn't immediately obvious that the In/Out nodes can be connected to multiple wires, made the first few rounds harder to work thru.