Posted by Narishma 3 hours ago
The only real point of contention I see between the two is that this piece goes on to talk about how it's a selling point that RISC-V can be used for both low-end 10 cent microcontrollers, and high-end multi-core processors running Linux. Personally I don't see the benefit of this since you're going to have to recompile your software anyway, and since all the RISC-V SBCs I'm aware of have significantly worse performance and efficiency than comparably priced ARM SBCs.
The benefit is a unified toolchain. Make a chip, get the entire software toolchain for free.
In the past if you made your own chip you had to write your own assembler, compiler, debugger, etc. Many manufacturers forked gcc but of course it's still a lot of work and the license isn't great (for them, not the user).
This universal compiler toolchain is massive benefit for both the chip makers and the end user.
So it is with the family of mutually incomprehensible ISAs called RISC-V.
And RISC-V is just starting here with shoestring design and fab budget. Wait till all engineering teams really adopt it like Tenstorrent and NextSilicon and so on.
I assume this is addressing
> and since all the RISC-V SBCs I'm aware of have significantly worse performance and efficiency than comparably priced ARM SBCs.
If so, could you point at specific SBCs that beat ARM SBC perf?
Any examples of this?
* Tenstorrent Ascalon has a neat optimization for certain LMUL>1 SIMD operations. LMUL=2 effectively unrolls the SIMD operation making it read two SIMD registers from every source and write two SIMD registers to the destination. There are however some instructions where LMUL=2 only needs to write to one registers, those are narrowing instructions (e.g. 64-bit to 32-bit truncation) and comparisons (which write to a LMUL=1 register with packed bits). When those SIMD instructions have to .vx form, which means one argument comes from a GPR, they now only need to write one SIMD register and need to read two SIMD registers. This matches what regular SIMD instructions need and because the silicon for the execution is much cheaper than register file ports, Ascalon can exexute these instructions in a single operation. So you can compare twice as many SIMD elements against a scalar, then you can against another SIMD register.
* Ventana (now under Qualcomm) talked a tiny bit about their fetch-block-optimizer and something that sounded like a L1i-trace cache. The fetch-block-optimizer would go to certain hot L1i entries and "optimize" them, with agressive instruction fusion including fusion of non-adjacent instructions.
* NextSilicon: Idk any details yet, but they said they handled RVC without increasing latency and that they've found a good solution for implement RVV and especially LMUL, which is a challange in out-of-order designs.
* OpenXiangShan: The fastes open-source CPU, is working on doing 2-ahead instruction fetch (the thing Zen5 added).
Now that being said, Ventana was bought by Qualcomm, we know the RISC-V team is still alive, but who knows if we'll ever see anything from that outside of Qualcomm?
The Tenstorrent Ascalon devboard is way behind schedule and on 12nm TSMC instead of a 4nm node the processor was designed for and is now supposed to clock at 1.38GHz. Though I think the delay has more to do with TT management problems then with the actual design.
While the scalar part of OpenXiangShan looks really good, the RVV imolementation is currently basically unusable. They want to have fix for the problems until the end of the year, but we'll have to see.
The improvement is entirely "we don't have to pay ARM"
I don't get how both things can be true. The cost to ship something to Trinidad and Tobago has nothing to do with whether it's ARM or RISC-V; shipping the same weight of either kind of chips should cost exactly the same amount. Yes, maybe the chip cost itself of a particular ARM-based model is $0.15 while the equivalent RISC-V chip costs $0.10, but if the issue (for him and other people who live outside US/Europe) is that shipping costs are orders of magnitude more expensive than the thing being shipped, that chip-cost difference becomes irrelevant.
I think he does make a great point about how fragmentation does give you better optionality: ARM is sort of like cable TV where you have a small number of product categories that each bundle a particular set of features, whereas with RISC-V you design something bespoke that does exactly what you need and nothing more. But again, this isn't going to affect shipping costs.
> From that position, the difference between a ten cent part and a one dollar part is not a rounding error and it is not a detail you get to wave past on the way to the interesting discussion about encodings
Yet earlier:
> I pay anywhere from US $60 to US $200 to ship one dollar chips that people everywhere else get free shipping on
Seems to me that the difference between a 10c chip and a $1 chip are a rounding error when the shipping cost dominates so much?
> The students I want to teach are in the same position, and so are the ones in Nigeria and Bangladesh
It does not take $60 to ship small sub $1 chips from Asia to Nigeria/Bangladesh. These two countries are all on global trade routes (both supply and demand) and the expensive last mile delivery costs are fairly low there too.
The typical bay area centric take has the following vibe:
1. I am among the group of most open minded people
2. I admit mistakes, but I don't change my view, that means I may make the same mistakes next time on a different concrete cases
3. Morally I am among the least corrupted
4. I work for the moderately morally questionable firms with nice paychecks, but my moral views are not tainted a bit
5. I never think on the other's perspectives
https://www.astralcodexten.com/p/the-foothills-of-bay-area-h...
My favorite bit, I think (along with the running gag of the constant use cases/connections that somehow pop up for Epstart’s founder):
> “Would you like to hear more about how copying AI tics helps me keep conversations going?”
> “Uh, sure - wait! No!” You break off and turn around as fast as you can.
If the other entries in the series are anywhere near as good, I’ll have some reading to do now.
Bangladesh is a country in Asia...
In my experience, the only demographic who complains about “Asia = east Asia” are people from South Asia, aka Indians/desis
So don't even try to find how expensive is bring these to Brazil. Even the $5 orders from JLCPCB become infeasible for hobbyists here due to all the roadblocks.
HN hasn't been Bay Area centric in years. Honestly, most comments and usership on the platform seems to now align with SWE culture in DACH and CEE.
Presumed RISC-V hate is a perfect example of that - the UCs and CSUs have been using RISC-V in their curriculum since the 2010s becuase Patterson is faculty at Cal and most CompArch courses in both systems have been using RISC-V as a result because 61a/b/c are often used as the benchmark curricula wise. An entire generation of Californian computer engineers have been RISC-V fluent as a result.
The hivemind assumption that HN's user base is "venture capital", "tech bro", "founders", and "Silicon Valley" is around 5 years out of date.
Anecdotally, the vast majority of younger (below 30) founders, engineers, VCs, and builders in the Bay have either not heard of HN or quit it within weeks due to toxicity.
I honestly do not get this at all. HN remains very US-centric to me, and especially centric to the mindshare of the Bay Area's IRL conversations, and apart from some takes on tech rights, does not really remind me of my experience in DACH.
>> HN remains very US-centric
Bay Area != US
The Bay Area is its own microcosm of culture and philosophy that diverges significantly from much of the US.
Not making a statement on how prevalent either are on HN, but Bay Area is very much not equivalent to the US.
Extremely. The valley/startup lens is absolutely the dominant one.
The majority of HN's usership, posting, and comment activity occurs during peak EU work hours (3am-9am), stylistic patterns that are common for German-, French, and Polish-native speakers are increasingly prominent (eg. periods and spaces instead of commas in numbers, spacing between quotation marks and words, failing to use context clues to infer timezone), and the fact that IRL conversation topics in the Bay Area tech scene are entirely different from those on HN shows a massive divergence in userbase.
HN "Who wants to get hired" threads are a good example of that as well.
I'd recommend deep diving in the HN scrape dataset on HuggingFace [0]. The site has diverged heavily compared to 2018 or 2012.
[0] - https://huggingface.co/datasets/open-index/hacker-news
" RL conversation topics in the Bay Area tech scene are entirely different from those on HN shows a massive divergence in userbase. " Any proof?
I like to encounter discussions about German digital health system or the German start up system or neo2. I've never seen them so I doubt it.
Also almost no debates about Polish stuff (Hello neigbours!)
fwiw, my experience is similar. hn has not been about startups, vc funding, or anything in that space for quite a while.
to paraphrase a classic, this place is like a memory of the forum we used to love, and the memory is fading.
Well, this place (wherever you are) is like a memory of the world we used to love, and the memory is fading... Definitely true too.
You can't expect a place tightly connected to a changing world to stay the same.
His criticisms are entirely valid, because why can't the the thing that has a free spec and will likely dominate that space ... also be good too? Can't we have all the nice things?
And while things has died down a lot in the past few years, there is a reason why I wrote the line.
"You do not criticise The Rusted Holy Grail and the Riscy Silver Bullet."
Though it feels a bit strange that "I have exceeded the allowed number of requests. (500 times)" when I first clicked the article and I'm pretty sure I don't share the ip of my self-hosted VPN with anyone.
You have exceeded the allowed number of requests. Your Requests: 500. Request Limit: 500 per minute. Tip: Please wait 60 seconds before trying again.
A 3rd World Embedded Engineer Learns About Caching Generated HTML The Hard Way.
Maybe I'm missing something important so far...
It definitely could have gone with a less abrasive tone (as entertaining as it is), so it's no wonder it's getting some pushback.