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Posted by iopapa 12 hours ago

Can AI design circuit boards yet?(eebench.org)
238 points | 144 commentspage 4
amelius 12 hours ago|
I'm excited by the option in Astra to route PCBs.

The next pain-point is sourcing the components from Digikey, LCSC, etc., and finding suitable substitutes if necessary.

Of course this assumes the LLMs can already read datasheets because that's the biggest pain-point in designing electronics. It's like filling out tax forms.

Finally it would be great if LLMs could extract simulation models from datasheets!

thesz 12 hours ago||

  > I'm excited by the option in Astra to route PCBs.
[1] https://en.wikipedia.org/wiki/Eurisko

Eurisko was used for VLSI chip design, then used rules discovered there to design TCS Traveler winning fleet.

It is unbelievable how artificial intelligence walk in circles.

thenthenthen 6 hours ago|||
Apparently this can source from LCSC: https://github.com/mixelpixx/KiCAD-MCP-Server Now how to hook it up to my Tencent ai thing…
iopapa 11 hours ago|||
Sourcing parts has been a huge motivation for this. We are still pretty jarred by the supply chain crisis a few years ago. Having the ability to formally verify that an alternative part fulfills the original design constraints is huge.

Not sure whether you played with llm datasheet extraction lately, but they are working their way up there. Even started reasoning about curves and footnotes.

Where do you think is the biggest pain point: part discovery, datasheet verification or substitute determination?

nickff 12 hours ago||
Routing is the easiest part of layout, and there have been auto-routers (which mostly worked) for a long time now; the difficult task is in placing components, and adjusting those placements.
amelius 12 hours ago||
Sure, I was just using "route" to mean also floorplanning because that's what Astra's routing tool also does. Not sure how they name it. Sorry if I was sloppy.
nickff 12 hours ago||
Not at all, but the term for routing and placing the components is ‘layout’. Floorplanning usually refers to the laying out of larger blocks of the circuit (with the blocks themselves already having been laid-out).
amelius 12 hours ago||
Yes but I'm not so concerned with how people name these steps.
dubbie99 12 hours ago||
I have found that AI is great for sorting out your libraries, drawing and helping double check footprints managing your BOM. I still draw my schematics and layout my boards. I haven’t found it any good for those tasks yet. There are too many stupid errors it makes. I do get it to review my work though and often it catches things I have missed.
dennis16384 12 hours ago||
If you give it a real solver to drive and business constraints to operate under, it will do pretty good job (which is to map your business rules to constraints and balanced costs, develop deterministic tests, probabilistic tests, acceptance gates, all boring stuff).
iopapa 11 hours ago|
Really excited about constraint solvers making a comeback! Especially after seeing Z3 getting a mention in anthropics fermat post. EEbench is using atopile's internal constraint solver for engineering parameters (think operating temperature, voltage ranges, stacked tolerances etc).
extralongdivisi 7 hours ago||
Very limited study.

A lot of datasheets are inaccessible without signing an NDA. Even if you're a VC-backed enterprise, some unnamed chip vendors will tell you to pound sand if you're less than 8 figures of annual revenue.

Worse, many recommendations in datasheets were written in the 80s, overkill for many applications, or completely wrong and won't be updated until an errata is published 6 months later. Given current workflows, I don't see how AI would help designing a PCB with an alpha chip that's doing anything remotely novel.

More to the articles point, AI designing ASICs or other Verilog/HDL defined components could be very interesting use case

lefra 1 hour ago||
> A lot of datasheets are inaccessible without signing an NDA

Only for very high-end stuff, where just designing the board around the chip needs a team of engineers.

edg5000 2 hours ago||
What kind of chips are you talking about? I guess most ARM SoCs and maybe RAM/ROM ICs?
ccpc 8 hours ago||
I'm finishing my bachelor's degree in radio electronics and instrument engineering. I've been using AI models to help me understand various concepts, but I want to say that, for now, they aren't ready for serious development.
edg5000 2 hours ago|
What makes you think that? They're great at reading datasheets and creating schematics in my experience. Layout I've been doing myself though, with the AI evaluating. I'll eventually delegate that as well. For schematics I use Skidl and some custom binding generators.
cmiles8 12 hours ago||
Have tried this a few times. While AI has been helpful in talking through component choices and other topics, it’s consistently been a spectacular fail each time in actually designing the board.

I’ve had similar results asking AI to design 3D models for 3D printing.

“Coach me on optimizing error on my printer”… helps.

“Build me a print ready file to these specs.”… it’s like a drunk cat attacked my computer. Just confidently puts out total nonsense.

sitzkrieg 11 hours ago|
LLMs like to fail spectacularly at real life measurement and not tell you about it as well
sillypuddy 10 hours ago||
Is this basically what https://www.diode.computer/ is doing?
tdeck 7 hours ago|
It's a bit curious that every image of the boards on their website looks like a render.
AdriaanvRossum 12 hours ago||
I know a startup [1] that tries to accomplish this.

[1] https://www.schematik.io/

iopapa 11 hours ago||
Love what samuel and his team are building over in the Netherlands! Always thought it would be fun if there was a more beginner friendly version of atopile [1].

[1] https:/atopile.io/

samuelbeek 11 hours ago|||
Mostly focused on BOM, schematics, and firmware now but slowly expanding to circuit boards if we feel we can deliver real value there. Early experiments with Astra are promising
maxdo 12 hours ago||
Love the democratization of access. Still curious how this is better vs gpt 6 astra or grok 4.7 in the future trained on spacex problems ?
NotThereYet 4 hours ago||
No because text models can’t spatially design and image models can’t spell
conorcleary 9 hours ago|
It's going to tell us that boards are inefficient and to start different
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